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HDL Implementation & Performance Comparison of Various Filtering Techniques Using FPGA (Record no. 129654)

MARC details
000 -LEADER
fixed length control field 00602nam a2200169 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 240924b |||||||| |||| 00| 0 eng d
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Ch.Sravana Vaidehi
245 ## - TITLE STATEMENT
Title HDL Implementation & Performance Comparison of Various Filtering Techniques Using FPGA
300 ## - PHYSICAL DESCRIPTION
Extent 45-54
654 ## - SUBJECT ADDED ENTRY--FACETED TOPICAL TERMS
Subject <a href="Matlab">Matlab</a>
-- <a href="Filtering Techniques">Filtering Techniques</a>
-- <a href="FPGA">FPGA</a>
-- <a href="VGA">VGA</a>
-- <a href="Cadence RTL Compiler ">Cadence RTL Compiler </a>
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name B.Murli Krishna
-- G.L Madhumati
-- N.Kalyan
773 0# - HOST ITEM ENTRY
Host Biblionumber 80273
Host Itemnumber 109586
Place, publisher, and date of publication New Delhi
Title Indian Journal of Advances in Communication Engineering
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Journal Article
773 0# - HOST ITEM ENTRY
-- JP29
942 ## - ADDED ENTRY ELEMENTS (KOHA)
-- ddc
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Location (home branch) Sublocation or collection (holding branch) Date acquired Koha issues (times borrowed) Piece designation (barcode) Koha date last seen Price effective from Koha item type
    Dewey Decimal Classification     SNDT Juhu SNDT Juhu 24/09/2024   JP29.5 24/09/2024 24/09/2024 Journal Article