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Design and Analysis of High Speed Phase Frequency Detector with Zero Dead Zone in PLL (Record no. 132580)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01708nam a2200133 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 250825b |||||||| |||| 00| 0 eng d |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Peta Guruprakash Kumar |
| 245 ## - TITLE STATEMENT | |
| Title | Design and Analysis of High Speed Phase Frequency Detector with Zero Dead Zone in PLL |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | p1190-1198 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. biblio.abstract | This paper presents a proposed phase frequency detector (PFD) designed by using the 180-nm CMOS process. Adding an extra buffer to the typical D flipflop-based PFD solves the dead zone (DZ) problem, however the frequency of operation is reduced. The proposed design of PFD eliminates the dead zone (DZ) and reduces the blind zone (BZ) significantly by developing the independent relationship between the blind zone (BZ) and the dead zone (DZ). Moreover, the proposed architecture helps to increase the operating frequency compared to the conventional architecture. The reset time of the proposed PFD requires one NAND gate, one AND gate, and an OR gate, whereas conventional PFDs require one D flipflop, one AND gate, and a delay element, which limits the frequency of operation in conventional architecture. The proposed architecture achieves 135 ps of reset time and 95 ps of delay time at the maximum operating frequency of 4.3 GHz. The phase noise of the proposed architecture is −143.2 dBc/Hz with 1 MHz offset at 4 GHz. The PLL is designed using the proposed PFD architecture with an reference frequency of 4 GHz and the phase noise is −110 dBc/Hz at a 1.5 MHz offset frequency. |
| 654 ## - SUBJECT ADDED ENTRY--FACETED TOPICAL TERMS | |
| Subject | <a href="Blind zone (BZ)">Blind zone (BZ)</a> |
| -- | <a href="Dead zone (DZ)">Dead zone (DZ)</a> |
| -- | <a href="Phase frequency detector (PFD">Phase frequency detector (PFD</a> |
| -- | <a href=")Phase locked loop (PLL)">)Phase locked loop (PLL)</a> |
| 773 0# - HOST ITEM ENTRY | |
| Host Biblionumber | 80269 |
| Host Itemnumber | 113443 |
| Place, publisher, and date of publication | New Delhi IETE |
| Title | IETE Journal of Research |
| International Standard Serial Number | 0377-2063 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Journal Article |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Location (home branch) | Sublocation or collection (holding branch) | Date acquired | Koha issues (times borrowed) | Piece designation (barcode) | Koha date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | SNDT Juhu | SNDT Juhu | 25/08/2025 | JP865.9 | 25/08/2025 | 25/08/2025 | Journal Article |