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Differential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic (Record no. 133185)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02161nam a2200157 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 251104b |||||||| |||| 00| 0 eng d |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Paksham Mahajan |
| 245 ## - TITLE STATEMENT | |
| Title | Differential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | Pages 373-383 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. biblio.abstract | Differential power analysis (DPA) stands as a formidable threat to cryptographic systems, exposing vulnerabilities in secure implementations and posing significant risks to sensitive information. Device power usage observations reveal details about the functions a device performs as well as the data it is processing. Substitution-box (S-box) circuits are employed to determine the relationship between cipher information and secret keys. However, because of more usage of power, attackers using DPA can exploit the S-box. In this paper, a secured and energy-efficient S-box circuit is implemented and proposed using CMOS transmission gate (TG) logic, and it is verified that it is DPA-resistant. Results reveal that CMOS TG-based S-box circuit occupies less area, dissipates less energy and requires lower power consumption in contrast to the standard CMOS and other existing logic families that are resistant to DPA attack. Security parameters, viz., normalized energy deviation and normalized standard deviation values obtained reveal that the power consumption values are uniform, and the circuit is resistant against DPA attack, making it suitable for use in various applications like smart cards, sensors, hardware IoT devices, etc. Cadence EDA tools have been used for designing of S-box circuit using a 180 nm CMOS technology node. |
| 654 ## - SUBJECT ADDED ENTRY--FACETED TOPICAL TERMS | |
| Subject | <a href="Adiabatic Logic">Adiabatic Logic</a> |
| -- | <a href="CMOS transmission gate logic">CMOS transmission gate logic</a> |
| -- | <a href="Differential power analysis">Differential power analysis</a> |
| -- | <a href="Field effect transistor">Field effect transistor</a> |
| -- | <a href="ormalized energy deviation">ormalized energy deviation</a> |
| -- | <a href="Normalized standard deviation">Normalized standard deviation</a> |
| -- | <a href="Power consumption">Power consumption</a> |
| -- | <a href="Side-channel attacks">Side-channel attacks</a> |
| -- | <a href="Simple power analysis">Simple power analysis</a> |
| -- | <a href="Substitution-box">Substitution-box</a> |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Rajeevan Chandel |
| 773 0# - HOST ITEM ENTRY | |
| Host Biblionumber | 133184 |
| Host Itemnumber | 114371 |
| Main entry heading | Mohammad Ehsan Sahami |
| Title | Proposing an Efficient Method for Resource Allocation in the IoT Devices based on Fog Computing in Face Detection Allocations |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Journal Article |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Location (home branch) | Sublocation or collection (holding branch) | Date acquired | Koha issues (times borrowed) | Piece designation (barcode) | Koha date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | SNDT Juhu | SNDT Juhu | 04/11/2025 | JP980.5 | 04/11/2025 | 04/11/2025 | Journal Article |