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Performance Evaluation and Stability Analysis of Gate-All-Around Junctionless Transistor Based 6T SRAM Memory Cell (Record no. 133186)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01824nam a2200157 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 251104b |||||||| |||| 00| 0 eng d |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Raj Sambhav |
| 245 ## - TITLE STATEMENT | |
| Title | Performance Evaluation and Stability Analysis of Gate-All-Around Junctionless Transistor Based 6T SRAM Memory Cell |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | Pages 384-392 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. biblio.abstract | In this work, the suitability and linearity of a Gate-All-Around Junctionless Transistor (GAA-JLT) is evaluated for designing of high reliable 6T SRAM memory cell. The analysis is also carried out for designing of GAA-JLT based CMOS inverter which demonstrate the robust noise margins. The noise margin gives insights about the efficacy of GAA-JLT CMOS inverters for digital circuit applications, particularly for memory applications. Static noise margin data for 6T SRAMs based on GAA JLT are included and compared against published work to support the findings. The higher SNM values obtained in the GAA JLT-based SRAM cell indicate enhanced stability during SRAM operations. Additionally, the paper investigates the impact of Word-Line Voltage Modulation and Supply Voltage Modulation on SNM stability. Both the design of the device and circuit implementation have been performed using ATLAS 3-D simulator. Mixed-mode simulation was used for circuit simulation. Overall, this research underscores the promise of GAA-JLT in digital circuits, highlighting its potential to improve stability, particularly in memory contexts. |
| 654 ## - SUBJECT ADDED ENTRY--FACETED TOPICAL TERMS | |
| Subject | <a href="Static random access memory (SRAM)">Static random access memory (SRAM)</a> |
| -- | <a href="Gate-all-around MOSFET">Gate-all-around MOSFET</a> |
| -- | <a href="Junctionless transistor">Junctionless transistor</a> |
| -- | <a href="CMOS inverter">CMOS inverter</a> |
| -- | <a href="Reliability">Reliability</a> |
| -- | <a href="Stability">Stability</a> |
| -- | <a href="Static noise margin">Static noise margin</a> |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Yogesh Pratap |
| 773 0# - HOST ITEM ENTRY | |
| Host Biblionumber | 133185 |
| Host Itemnumber | 114372 |
| Main entry heading | Paksham Mahajan |
| Title | Differential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Journal Article |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Location (home branch) | Sublocation or collection (holding branch) | Date acquired | Koha issues (times borrowed) | Piece designation (barcode) | Koha date last seen | Price effective from | Koha item type |
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| Dewey Decimal Classification | SNDT Juhu | SNDT Juhu | 04/11/2025 | JP980.6 | 04/11/2025 | 04/11/2025 | Journal Article |