TY  - BOOK
AU  - Madugula Naga Vishnavi 
AU  - V.Priyadarshini 
TI  - Recital Analysis of 64 Bit Unsigned Data Using Various Adders 
KW  - CLAA
KW  - CSLA
KW  - CSA Adder
KW  - Verilog HDL Language
KW  - Xilinx simulator
KW  - Area
KW  - Delay
ER  -