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100			_aPaksham Mahajan
245			_aDifferential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic
300			_aPages 373-383
520			_aDifferential power analysis (DPA) stands as a formidable threat to cryptographic systems, exposing vulnerabilities in secure implementations and posing significant risks to sensitive information. Device power usage observations reveal details about the functions a device performs as well as the data it is processing. Substitution-box (S-box) circuits are employed to determine the relationship between cipher information and secret keys. However, because of more usage of power, attackers using DPA can exploit the S-box. In this paper, a secured and energy-efficient S-box circuit is implemented and proposed using CMOS transmission gate (TG) logic, and it is verified that it is DPA-resistant. Results reveal that CMOS TG-based S-box circuit occupies less area, dissipates less energy and requires lower power consumption in contrast to the standard CMOS and other existing logic families that are resistant to DPA attack. Security parameters, viz., normalized energy deviation and normalized standard deviation values obtained reveal that the power consumption values are uniform, and the circuit is resistant against DPA attack, making it suitable for use in various applications like smart cards, sensors, hardware IoT devices, etc. Cadence EDA tools have been used for designing of S-box circuit using a 180 nm CMOS technology node.
654			_aAdiabatic Logic _aCMOS transmission gate logic _aDifferential power analysis _aField effect transistor _aormalized energy deviation _aNormalized standard deviation _aPower consumption _aSide-channel attacks _aSimple power analysis _aSubstitution-box
700			_aRajeevan Chandel
773	0		_0133184 _9114371 _aMohammad Ehsan Sahami _tProposing an Efficient Method for Resource Allocation in the IoT Devices based on Fog Computing in Face Detection Allocations
942			_cJA
999			_c133185 _d133185