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Differential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic
Paksham Mahajan
Differential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic - Pages 373-383
Differential power analysis (DPA) stands as a formidable threat to cryptographic systems, exposing vulnerabilities in secure implementations and posing significant risks to sensitive information. Device power usage observations reveal details about the functions a device performs as well as the data it is processing. Substitution-box (S-box) circuits are employed to determine the relationship between cipher information and secret keys. However, because of more usage of power, attackers using DPA can exploit the S-box. In this paper, a secured and energy-efficient S-box circuit is implemented and proposed using CMOS transmission gate (TG) logic, and it is verified that it is DPA-resistant. Results reveal that CMOS TG-based S-box circuit occupies less area, dissipates less energy and requires lower power consumption in contrast to the standard CMOS and other existing logic families that are resistant to DPA attack. Security parameters, viz., normalized energy deviation and normalized standard deviation values obtained reveal that the power consumption values are uniform, and the circuit is resistant against DPA attack, making it suitable for use in various applications like smart cards, sensors, hardware IoT devices, etc. Cadence EDA tools have been used for designing of S-box circuit using a 180 nm CMOS technology node.
Adiabatic Logic
CMOS transmission gate logic
Differential power analysis
Field effect transistor
ormalized energy deviation
Normalized standard deviation
Power consumption
Side-channel attacks
Simple power analysis
Substitution-box
Differential Power Analysis Resistant Secured S-Box Circuit Using CMOS Transmission Gate Logic - Pages 373-383
Differential power analysis (DPA) stands as a formidable threat to cryptographic systems, exposing vulnerabilities in secure implementations and posing significant risks to sensitive information. Device power usage observations reveal details about the functions a device performs as well as the data it is processing. Substitution-box (S-box) circuits are employed to determine the relationship between cipher information and secret keys. However, because of more usage of power, attackers using DPA can exploit the S-box. In this paper, a secured and energy-efficient S-box circuit is implemented and proposed using CMOS transmission gate (TG) logic, and it is verified that it is DPA-resistant. Results reveal that CMOS TG-based S-box circuit occupies less area, dissipates less energy and requires lower power consumption in contrast to the standard CMOS and other existing logic families that are resistant to DPA attack. Security parameters, viz., normalized energy deviation and normalized standard deviation values obtained reveal that the power consumption values are uniform, and the circuit is resistant against DPA attack, making it suitable for use in various applications like smart cards, sensors, hardware IoT devices, etc. Cadence EDA tools have been used for designing of S-box circuit using a 180 nm CMOS technology node.
Adiabatic Logic
CMOS transmission gate logic
Differential power analysis
Field effect transistor
ormalized energy deviation
Normalized standard deviation
Power consumption
Side-channel attacks
Simple power analysis
Substitution-box