SNDT WOMEN'S UNIVERSITY
BMK Knowledge Resource Centre
Vithaldas Vidyavihar, Juhu Tara Road,
Santacruz (West) Mumbai - 400049
Real Time Delay Application for Digital Circuits with Peripheral based Digital Clock using FPGA
Description: 69-78Subject(s): In: Indian Journal of Advances in Communication Engineering New Delhi| Item type | Current library | Status | Barcode | |
|---|---|---|---|---|
| Journal Article | SNDT Juhu | Available | JP29.7 | |
| Periodicals | SNDT Juhu | Available | JP29 |
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