This paper presents a proposed phase frequency detector (PFD) designed by using the 180-nm CMOS process. Adding an extra buffer to the typical D flipflop-based PFD solves the dead zone (DZ) problem, however the frequency of operation is reduced. The proposed design of PFD eliminates the dead zone (DZ) and reduces the blind zone (BZ) significantly by developing the independent relationship between the blind zone (BZ) and the dead zone (DZ). Moreover, the proposed architecture helps to increase the operating frequency compared to the conventional architecture. The reset time of the proposed PFD requires one NAND gate, one AND gate, and an OR gate, whereas conventional PFDs require one D flipflop, one AND gate, and a delay element, which limits the frequency of operation in conventional architecture. The proposed architecture achieves 135 ps of reset time and 95 ps of delay time at the maximum operating frequency of 4.3 GHz. The phase noise of the proposed architecture is −143.2 dBc/Hz with 1 MHz offset at 4 GHz. The PLL is designed using the proposed PFD architecture with an reference frequency of 4 GHz and the phase noise is −110 dBc/Hz at a 1.5 MHz offset frequency.