In this work, the suitability and linearity of a Gate-All-Around Junctionless Transistor (GAA-JLT) is evaluated for designing of high reliable 6T SRAM memory cell. The analysis is also carried out for designing of GAA-JLT based CMOS inverter which demonstrate the robust noise margins. The noise margin gives insights about the efficacy of GAA-JLT CMOS inverters for digital circuit applications, particularly for memory applications. Static noise margin data for 6T SRAMs based on GAA JLT are included and compared against published work to support the findings. The higher SNM values obtained in the GAA JLT-based SRAM cell indicate enhanced stability during SRAM operations. Additionally, the paper investigates the impact of Word-Line Voltage Modulation and Supply Voltage Modulation on SNM stability. Both the design of the device and circuit implementation have been performed using ATLAS 3-D simulator. Mixed-mode simulation was used for circuit simulation. Overall, this research underscores the promise of GAA-JLT in digital circuits, highlighting its potential to improve stability, particularly in memory contexts.